A symbolic algorithm for low-power sequential synthesis
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Efficient state classification of finite state Markov chains
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computational kernels and their application to sequential power optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Theoretical bounds for switching activity analysis in finite-state machines
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Kernel-based power optimization of RTL components: exact and approximate extraction algorithms
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Non-stationary effects in trace-driven power analysis
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Implicit enumeration of strongly connected components
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Trace-driven steady-state probability estimation in FSMs with application to power estimation
Proceedings of the conference on Design, automation and test in Europe
Process algebra for performance evaluation
Theoretical Computer Science
Computing strongly connected components in a linear number of symbolic steps
SODA '03 Proceedings of the fourteenth annual ACM-SIAM symposium on Discrete algorithms
Advances in Model Representations
PAPM-PROBMIV '01 Proceedings of the Joint International Workshop on Process Algebra and Probabilistic Methods, Performance Modeling and Verification
Out-of-Core Solution of Large Linear Systems of Equations Arising from Stochastic Modelling
PAPM-PROBMIV '02 Proceedings of the Second Joint International Workshop on Process Algebra and Probabilistic Methods, Performance Modeling and Verification
Symbolic Model Checking of Probabilistic Processes Using MTBDDs and the Kronecker Representation
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Approximate Symbolic Model Checking of Continuous-Time Markov Chains
CONCUR '99 Proceedings of the 10th International Conference on Concurrency Theory
Performance Analysis of Asynchronous Circuits Using Markov Chains
Concurrency and Hardware Design, Advances in Petri Nets
Bisimulation Algorithms for Stochastic Process Algebras and Their BDD-Based Implementation
ARTS '99 Proceedings of the 5th International AMAST Workshop on Formal Methods for Real-Time and Probabilistic Systems
ProbVerus: Probabilistic Symbolic Model Checking
ARTS '99 Proceedings of the 5th International AMAST Workshop on Formal Methods for Real-Time and Probabilistic Systems
Handbook of automated reasoning
Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
A Probabilistic Method for the Computation of Testability of RTL Constructs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
IEEE Transactions on Computers
Gate-level simulation of quantum circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Particle-based methodology for representing mobile ad-hoc networks
InterSense '06 Proceedings of the first international conference on Integrated internet ad hoc and sensor networks
Soft error rate analysis for sequential circuits
Proceedings of the conference on Design, automation and test in Europe
Improving testability and soft-error resilience through retiming
Proceedings of the 46th Annual Design Automation Conference
Signature-based SER analysis and design of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RECOMB'07 Proceedings of the 11th annual international conference on Research in computational molecular biology
Markov anomaly modeling for trust management in variable threat environments
Proceedings of the 48th Annual Southeast Regional Conference
Efficient algorithms for multilevel power estimation of VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Symbolic computation of strongly connected components and fair cycles using saturation
Innovations in Systems and Software Engineering
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Regarding finite state machines as Markov chains facilitates the application of probabilistic methods to very large logic synthesis and formal verification problems. In this paper we present symbolic algorithms to compute the steady-state probabilities for very large finite state machines (up to 1027 states). These algorithms, based on Algebraic Decision Diagrams (ADD's)-an extension of BDD's that allows arbitrary values to be associated with the terminal nodes of the diagrams-determine the steady-state probabilities by regarding finite state machines as homogeneous, discrete-parameter Markov chains with finite state spaces, and by solving the corresponding Chapman-Kolmogorov equations. We first consider finite state machines with state graphs composed of a single terminal strongly connected component; for this type of system we have implemented two solution techniques: One is based on the Gauss-Jacobi iteration, the other one is based on simple matrix multiplication. Then we extend our treatment to the most general case of systems which can be modelled as finite state machines with arbitrary transition structures; here our approach exploits structural information to decompose and simplify the state graph of the machine. We report experimental results obtained for problems on which traditional methods fail