Re-encoding sequential circuits to reduce power dissipation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Low power state assignment targeting two-and multi-level logic implementations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Activity-sensitive architectural power analysis for the control path
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A symbolic algorithm for low-power sequential synthesis
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
High-level area and power estimation for VLSI circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Achievable bounds on signal transition activity
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Entropic bounds on FSM switching
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Power estimation of behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
Trace-driven steady-state probability estimation in FSMs with application to power estimation
Proceedings of the conference on Design, automation and test in Europe
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
SYCLOP: Synthesis of CMOS Logic for Low Power Applications
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Information theoretic measures for power analysis [logic design]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Markovian analysis of large finite state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Regression-based RTL power models for controllers
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
High-fidelity Markovian power model for protocols
Proceedings of the Conference on Design, Automation and Test in Europe
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The objective of this paper is to provide lower and upper bounds for the switching activity on the state lines in Finite State Machines (FSMs). Using a Markov chain model for the behavior of the states of the FSM, we derive theoretical bounds for the average Hamming distance on the state lines which are valid irrespective of the state encoding used in the final implementation. Such lower and upper bounds, in addition to providing a target for any state assignment algorithm, can also be used as parameters in a high-level model of power, and thus provide an early indication about the performance limits of the target FSM. Experimental results obtained for the mcnc'91 benchmark suite show that our bounds are tighter than the bounds reported previously by other researchers and can be effectively used in a high-level power estimation framework.