High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Hierarchical sequence compaction for power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Analytical estimation of transition activity from word-level signal statistics
DAC '97 Proceedings of the 34th annual Design Automation Conference
Achievable bounds on signal transition activity
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Fast power estimation for deterministic input streams
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Towards the capability of providing power-area-delay trade-off at the register transfer level
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Theoretical bounds for switching activity analysis in finite-state machines
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
The petrol approach to high-level power estimation
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Energy-efficiency in presence of deep submicron noise
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Parameterized RTL power models for combinational soft macros
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Regression-based RTL power modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power estimation of behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
Trace-driven system-level power evaluation of system-on-a-chip peripheral cores
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Instruction-based system-level power evaluation of system-on-a-chip peripheral cores
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Least-square estimation of average power in digital CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic transformation for low-power synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Novel modeling techniques for RTL power estimation
Proceedings of the 2002 international symposium on Low power electronics and design
System-level exploration for pareto-optimal configurations in parameterized systems-on-a-chip
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Markov chain sequence generator for power macromodeling
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Conquering Uncertainty in Multiple-Valued Logic Design
Artificial Intelligence Review
Energy and peak-current per-cycle estimation at RTL
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Safe integration of parameterized IP
Integration, the VLSI Journal - Special issue: IP and design reuse
Energy Bounds for Fault-Tolerant Nanoscale Designs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Conquering uncertainty in multiple-valued logic design
Artificial intelligence in logic design
A path based modeling approach for dynamic power estimation
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Low Power VLSI Design Techniques - The Current State
Integrated Computer-Aided Engineering
FSM decomposition with application to FPGA synthesis
CompSysTech '09 Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing
| Hi-index | 0.03 |
This paper considers the problem of estimating the power consumption at logic and register-transfer levels of design from an information theoretical point of view. In particular, it is demonstrated that the average switching activity in the circuit can be calculated using either entropy or informational energy averages. For control circuits and random logic, the output entropy (informational energy) per bit is calculated as a function of the input entropy (informational energy) per bit and an implementation dependent information scaling factor. For data-path circuits, the output entropy (informational energy) is calculated from the input entropy (informational energy) using a compositional technique which has linear complexity in terms of the circuit size. Finally, from these input and output values, the entropy (informational energy) per circuit line is calculated and used as an estimate for the average switching activity. The proposed switching activity estimation technique does not require simulation and is thus extremely fast, yet produces sufficiently accurate estimates