PHIDEO: high-level synthesis for high throughput applications
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
An Integrated CAD Environment for Low-Power Design
IEEE Design & Test
Adaptive least mean square behavioral power modeling
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Towards a high-level power estimation capability [digital ICs]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Information theoretic measures for power analysis [logic design]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient RTL Power Estimation for Large Designs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
High-level macro-modeling and estimation techniques for switching activity and power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power Analysis of a General Convolution Algorithm Mapped on a Linear Processor Array
Journal of VLSI Signal Processing Systems
Hardware Accelerated Power Estimation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Power emulation: a new paradigm for power estimation
Proceedings of the 42nd annual Design Automation Conference
Scalable IC platform for smart cameras
EURASIP Journal on Applied Signal Processing
Estimating energy consumption for an MPSoC architectural exploration
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Delay constrained register transfer level dynamic power estimation
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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High-level power estimation is essential for designing complex low-power ICs. However, the lack of flexibility, or restriction to synthesizable code of previously presented high-level power estimation approaches limits their use. In this paper we present a novel, more general and flexible high-level power estimation approach, that avoids these limitations. Petrol, as we call it, is not limited to specialized application domains, synthesizable VHDL, or data path parts of a design. We show that glitches can be usefully modeled at higher levels of abstraction. The Petrol approach shows good correlation with gate-level power estimates. It is currently used for commercial designs.