High-level power estimation and the area complexity of Boolean functions
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Power macromodeling for high level power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Hierarchical sequence compaction for power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Analytical estimation of transition activity from word-level signal statistics
DAC '97 Proceedings of the 34th annual Design Automation Conference
High-level area and power estimation for VLSI circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Achievable bounds on signal transition activity
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Fast power estimation for deterministic input streams
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Towards the capability of providing power-area-delay trade-off at the register transfer level
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
The petrol approach to high-level power estimation
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Parallel mixed-level power simulation based on spatio-temporal circuit partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Energy-per-cycle estimation at RTL
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Parameterized RTL power models for combinational soft macros
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Regression-based RTL power modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power estimation of behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
A new method for constructing IP level power model based on power sensitivity
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Trace-driven system-level power evaluation of system-on-a-chip peripheral cores
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Instruction-based system-level power evaluation of system-on-a-chip peripheral cores
ISSS '00 Proceedings of the 13th international symposium on System synthesis
On gate level power optimization using dual-supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level exploration for pareto-optimal configurations in parameterized systems-on-a-chip
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy and peak-current per-cycle estimation at RTL
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-Level Power Analysis Methodology Applied to the AMBA AHB Bus
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Energy Bounds for Fault-Tolerant Nanoscale Designs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Power estimation for cycle-accurate functional descriptions of hardware
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Low Power VLSI Design Techniques - The Current State
Integrated Computer-Aided Engineering
Modeling the energy cost of applications on portable wireless devices
Proceedings of the 11th international symposium on Modeling, analysis and simulation of wireless and mobile systems
Power-Aware Design via Micro-architectural Link to Implementation
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Area and power efficient mismatched filters based on sidelobe inversion
Signal Processing
Reliability analysis of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power efficient co-simulation framework for a wireless application using platform based SoC
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Delay constrained register transfer level dynamic power estimation
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
UVM-based verification methodology for RFID-enabled smart-sensor systems
Analog Integrated Circuits and Signal Processing
| Hi-index | 0.03 |
We present a power estimation technique for digital integrated circuits that operates at the register transfer level (RTL). Such a high-level power estimation capability Is required in order to provide early warning of any power problems before the circuit-level design has been specified. With such early warning, the designer can explore design trade-offs at a higher level of abstraction than previously possible, reducing design time and cost. Our estimator is based on the use of entropy as a measure of the average activity to be expected in the final implementation of a circuit, given only its Boolean functional description. This technique has been implemented and tested on a variety of circuits. The empirical results to be presented are very promising and demonstrate the feasibility and utility of this approach