Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cycle-accurate macro-models for RT-level power analysis
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Power macromodeling for high level power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Node sampling: a robust RTL power modeling approach
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A new parameterizable power macro-model for datapath components
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Adaptive least mean square behavioral power modeling
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Towards a high-level power estimation capability [digital ICs]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Information theoretic measures for power analysis [logic design]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power Models for Semi-autonomous RTL Macros
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
RTL Estimation of Steering Logic Power
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Power Macro-Modelling for Firm-Macro
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
An Improved Power Macro-Model for Arithmetic Datapath Components
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Challenges for architectural level power modeling
Power aware computing
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We propose a new RTL power macromodel that is suitable for re-configurable, synthesizable soft-macros. The model is parameterized with respect to the input data size (i.e., bit-width), and can be automatically scaled with respect to different technology libraries and/or synthesis options. Scalability is obtained through a single additional characterizations run, and does not require the disclosure of any intellectual property. The model is derived from empirical analysis of the sensitivity of power on input statistics, input data size and technology. The experiments prove that, with limited approximation, it is possible to de-couple the effects on power of these three factors. The proposed solution is innovative, since no previous macromodel supports automatic technology scaling, and yields estimation errors within 15%.