Cycle-accurate macro-models for RT-level power analysis

A power macromodeling technique based on power sensitivity

DAC '98 Proceedings of the 35th annual Design Automation Conference

Node sampling: a robust RTL power modeling approach

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Estimation of power sensitivity in sequential circuits with power macromodeling application

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Non-stationary effects in trace-driven power analysis

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design

Parameterized RTL power models for combinational soft macros

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Characterization-free behavioral power modeling

Proceedings of the conference on Design, automation and test in Europe

Parameterized RTL power models for soft macros

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design

Energy estimation and optimization of embedded VLIW processors based on instruction clustering

Proceedings of the 39th annual Design Automation Conference

Probabilistic Bottom-Up RTL Power Estimation

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

Run-time energy estimation in system-on-a-chip designs

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

A path based modeling approach for dynamic power estimation

Proceedings of the 17th ACM Great Lakes symposium on VLSI

Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis

Proceedings of the International Conference on Computer-Aided Design