The multiflow trace scheduling compiler
The Journal of Supercomputing - Special issue on instruction-level parallelism
Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Instruction level power analysis and optimization of software
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
Power analysis and minimization techniques for embedded DSP software
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Techniques for low energy software
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Cycle-accurate macro-models for RT-level power analysis
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
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MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
ACM Computing Surveys (CSUR)
Instruction-level power estimation for embedded VLIW cores
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Lx: a technology platform for customizable VLIW embedded processing
Proceedings of the 27th annual international symposium on Computer architecture
Compiler optimization on instruction scheduling for low power
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Power exploration for embedded VLIW architectures
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Data Dependent Approach to Instruction Level Power Estimation
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Instruction Scheduling Based on Energy and Performance Constraints
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Software Power Estimation and Optimization for High Performance, 32-bit Embedded Processors
ICCD '98 Proceedings of the International Conference on Computer Design
Branch prediction techniques for low-power VLIW processors
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Proceedings of the 2003 ACM symposium on Applied computing
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Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
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Proceedings of the 14th ACM Great Lakes symposium on VLSI
Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors
Proceedings of the 14th ACM Great Lakes symposium on VLSI
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Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors
IEEE Transactions on Computers
Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
A quantitative study and estimation models for extensible instructions in embedded processors
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Instruction scheduling of VLIW architectures for balanced power consumption
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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ACM Transactions on Architecture and Code Optimization (TACO)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
EURASIP Journal on Applied Signal Processing
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International Journal of High Performance Computing and Networking
Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture
Journal of Signal Processing Systems
Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
ICATPN'06 Proceedings of the 27th international conference on Applications and Theory of Petri Nets and Other Models of Concurrency
Rule-Based power-balanced VLIW instruction scheduling with uncertainty
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Power Modeling for Heterogeneous Processors
Proceedings of Workshop on General Purpose Processing Using GPUs
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Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power modeling methodology is the key issue to define an effective energy-aware software optimisation strategy for state-of-the-art ILP (Instruction Level Parallelism) processors. The methodology is based on an energy model for VLIW processors that exploits instruction clustering to achieve an efficient and fine grained energy estimation. The approach aims at reducing the complexity of the characterization problem for VLIW processors from exponential, with respect to the number of parallel operations in the same very long instruction, to quadratic, with respect to the number of instruction clusters. Furthermore, the paper proposes a spatial scheduling algorithm based on a low-power reordering of the parallel operations within the same long instruction. Experimental results have been carried out on the Lx processor, a 4-issue VLIW core jointly designed by HPLabs and STMicroelectronics. The results have shown an average error of 1.9% between the cluster-based estimation model and the reference design, with a standard deviation of 5.8%. For the Lx architecture, the spatial instruction scheduling algorithm provides an average energy saving of 12%.