Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Power analysis and minimization techniques for embedded DSP software
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Microprocessor Architectures: From VLIW to Tta
Microprocessor Architectures: From VLIW to Tta
A Data Dependent Approach to Instruction Level Power Estimation
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
High-level software energy macro-modeling
Proceedings of the 38th annual Design Automation Conference
Power-aware modulo scheduling for high-performance VLIW processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Energy estimation and optimization of embedded VLIW processors based on instruction clustering
Proceedings of the 39th annual Design Automation Conference
Power exploration for embedded VLIW architectures
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Energy Estimation for Extensible Processors
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Instantaneous current modeling in a complex VLIW processor core
ACM Transactions on Embedded Computing Systems (TECS)
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application
SEA: fast power estimation for micro-architectures
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors
International Journal of High Performance Computing and Networking
Methodology for multi-granularity embedded processor power model generation for an ESL design flow
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Compiler and runtime support for predictive control of power and cooling
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A multi-granularity power modeling methodology for embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Processor energy characterization for compiler-assisted software energy reduction
Journal of Electrical and Computer Engineering
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In this paper, a power estimation methodology operating at the instruction-level is proposed. The methodology is tightly related to the characteristics of the system architecture, mainly in terms of one or more target processors, the memory sub-system, the system-level buses and the coprocessors. In this system-level framework, our main goal is to define a power model for CPU cores at the instruction-level. First, the proposed power model deals with a general five-stage pipeline processor architecture, then, the model is extended to VLIW processors. The derivation of a VLIW instruction-level power model results to be intractable from the point of view of spatial complexity (which grows exponentially w.r.t. the number of possible operations in the ISA). In order to tackle this complexity, a new kind of simplification, based on the original concept of separability of processor functional units, is introduced. The proposed system-level methodology is the first step toward a more general framework to support the design of power-oriented applications through hardware/software co-design.1