Model selection
Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient power estimation for highly correlated input streams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Module assignment for low power
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A power estimation framework for designing low power portable video applications
DAC '97 Proceedings of the 34th annual Design Automation Conference
Practical low power digital VLSI design
Practical low power digital VLSI design
IEEE Transactions on Computers
A new parameterizable power macro-model for datapath components
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Lower and upper bounds on the switching activity in scheduled data flow graphs
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Parameterized RTL power models for combinational soft macros
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A unified lower bound estimation technique for high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analytical estimation of signal transition activity from word-level statistics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level power modeling, estimation, and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Improved Power Macro-Model for Arithmetic Datapath Components
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
A multi-model engine for high-level power estimation accuracy optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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An approach for power modelling of parameterized, technology independent design components (firm-macros) is presented. Executable simulation models in form of C++ classes are generated by a systematic procedure that is based on statistical modelling and table look-up techniques. In contrast to other table look-up based approaches the proposed model separately handles the inputs of a component, and with this it allows to model the effects of corresponding joint-dependencies. In addition, a technique for the generation of executable models is presented. The generated models are optimized with respect to simulation performance and can be applied for power analysis and optimization tasks on the behavioral and architectural level. Results are presented for a number of test cases which show the good quality of the model.