Activity-sensitive architectural power analysis for the control path
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
A new parameterizable power macro-model for datapath components
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Power scalable processing using distributed arithmetic
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Application-driven processor design exploration for power-performance trade-off analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Power Macro-Modelling for Firm-Macro
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Framework for High-Level Power Estimation of Signal Processing Architectures
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
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This paper presents a power evaluation framework designedfor estimating power consumption of a new video telephonecompression standard, ITU-H.263, at the system level.A hierarchical,mixed-level simulation environment is built andcycle-accurate power macro-modeling is used for the architecturalpower evaluation.Experimental results show the effectivenessof the proposed framework and models.