Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A power estimation framework for designing low power portable video applications
DAC '97 Proceedings of the 34th annual Design Automation Conference
Power modeling for high-level power estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analytical estimation of signal transition activity from word-level statistics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Probabilistic Power Estimation for Digital Signal Processing Architectures
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
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A framework for high-level power estimation dedicated to the design of signal processing architectures is presented in this work. A strong emphasis lies on the integration of the power estimation into the regular design-flow and on keeping the modeling overhead low. This was achieved through an object-oriented design of the estimation tool. Main features are: an easy macromodule extension, the implementation of a Verilog HDL subset, and a moderate model complexity. Estimation results obtained using the framework for development of a discrete cosine transform compare to the deviation of power consumption imposed by their data dependency.