Probabilistic Power Estimation for Digital Signal Processing Architectures

Authors:
Achim Freimann
Affiliations:
-
Venue:
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Year:
2002

Citing 3
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Abstract

A method for estimating the power on architecture-level is described. Originally based on simulations with data sequences, the method is extended by an simulation-free approach. The statistical properties required for the underlying Dual-Bit-Type model are propagated through the circuit. The necessary computation formulas are presented. For both approaches, the model accuracy for base modules as for signal processing applications is comparably low.