A survey of optimization techniques targeting low power VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Information theoretic measures of energy consumption at register transfer level
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
A power macromodeling technique based on power sensitivity
DAC '98 Proceedings of the 35th annual Design Automation Conference
Estimation of power sensitivity in sequential circuits with power macromodeling application
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
A static estimation technique of power sensitivity in logic circuits
Proceedings of the 38th annual Design Automation Conference
IBM Journal of Research and Development
Automatic insertion of low power annotations in RTL for pipelined microprocessors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Towards a high-level power estimation capability [digital ICs]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Micro-architectural power macro-models dictate the power budget of a new chip design. Based on the early feasibility studies, power specification of new features are defined and then verified all through the design cycle. In this paper, we introduce a novel power-aware design paradigm that aligns power macro-models by mapping power-significant events at all levels of design hierarchy. We apply this paradigm on a state-of-the-art 65nm high-performance micro-processor and demonstrate significant benefits in power optimization at RTL implementation.Moreover, this approach facilitates a feedback loop from the design implementation to higher level (micro-architectural) power models and thus has built-in potential for more accurate power models.