A static estimation technique of power sensitivity in logic circuits

Authors:
Taewhan Kim;Ki-Seok Chung;C. L. Liu
Affiliations:
Dept. of EECS, KAIST Taejon, Korea;Design Technology, Intel Corporation, Santa Clara, CA;Dept. of CS, Tsing Hua Univ., Hsinchu, Taiwan R.O.C.
Venue:
Proceedings of the 38th annual Design Automation Conference
Year:
2001

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Abstract

In this paper, we study a new problem of statically estimating the power sensitivity of a given logic circuit with respect to the primary inputs. The power sensitivity defines the characteristics of power dissipation due to changes in state of primary inputs. Consequently, estimating the power sensitivity among the inputs is essential not only to measure the power consumption of the circuit efficiently but also to provide potential opportunities of redesigning the circuit for low power. In this context, we propose a fast and reliable static estimation technique for power sensitivity based on a new concept calledpower equations, which are then collectively transformed into a table calledpower table. Experimental data on MCNC benchmark examples show that the proposed technique is useful and effective in estimating power consumption. In summary, the relative error for the estimation of maximum power consumption is 9.4\% with a huge speed-up in simulation.