Maximum current estimation in CMOS circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Transition density, a stochastic measure of activity in digital circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Statistical estimation of the switching activity in digital circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
Maximum power estimation using the limiting distributions of extreme order statistics
DAC '98 Proceedings of the 35th annual Design Automation Conference
Non-stationary effects in trace-driven power analysis
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Maximum current estimation considering power gating
Proceedings of the 2001 international symposium on Physical design
A static estimation technique of power sensitivity in logic circuits
Proceedings of the 38th annual Design Automation Conference
Transient power management through high level synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Prediction of Power Requirements for High-Speed Circuits
Real-World Applications of Evolutionary Computing, EvoWorkshops 2000: EvoIASP, EvoSCONDI, EvoTel, EvoSTIM, EvoROB, and EvoFlight
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Vector extraction for average total power estimation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Maximum circuit activity estimation using pseudo-boolean satisfiability
Proceedings of the conference on Design, automation and test in Europe
Satisfiability models for maximum transition power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bounded delay timing analysis and power estimation using SAT
Microelectronics Journal
Statistical full-chip total power estimation considering spatially correlated process variations
Integration, the VLSI Journal
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Excessive instantaneous power consumption may reduce the reliability and performance of VLSI chips. Hence, to synthesize circuits with high reliability, it is imperative to efficiently obtain a precise estimation of the maximum power dissipation. However, due to the inherent input-pattern dependence of the problem, it is impractical to conduct an exhaustive search for circuits with a large number of primary inputs. Hence, the practical approach is to generate a tight lower bound and an upper bound for maximum power dissipation within a reasonable amount of central processing unit (CPU) time. In this paper, instead of using the traditional simulation-based techniques, we propose a novel approach to obtain a lower bound of the maximum power consumption using automatic test generation (ATG) technique. Experiments with MCNC and ISCAS-85 benchmark circuits show that our approach generates the lower bound with the quality which cannot be achieved using simulation-based techniques. In addition, a Monte Carlo-based technique to estimate maximum power dissipation is described. It not only serves as a comparison version for our ATG approach, but also generates a metric to measure the quality of a lower bound from a statistical point of view.