Temporal analysis for time-bounded causal digital systems
Temporal analysis for time-bounded causal digital systems
Simulation of digital circuits in the presence of uncertainty
Simulation of digital circuits in the presence of uncertainty
Peak power estimation using genetic spot optimization for large VLSI circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Satisfiability models and algorithms for circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Event propagation for accurate circuit delay calculation using SAT
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Bounded Delay Timing Analysis Using Boolean Satisfiability
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Accurate timing analysis using SAT and pattern-dependent delay models
Proceedings of the conference on Design, automation and test in Europe
Using SAT-based techniques in power estimation
Microelectronics Journal
Maximum power estimation for CMOS circuits using deterministic and statistical approaches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test pattern generation using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a satisfiability based approach that can be used for accurate estimation of both the critical delay and dynamic transition power consumption of circuits using an event propagation model. The accuracy of the model depends on the accuracy of the gate delays. The speed and efficiency of modern Boolean SAT solvers permits us to model complicated delay models like the Bounded Delay Model, which is better able to capture realistic variations in gate delays due to process variations and changes in operating conditions. We show that timing analysis with bounded delays yields a more accurate critical delay for a circuit than with fixed gate delays. In spite of the high complexity due to unpredictable gate delays, our SAT based approach gives good performance on benchmark circuits, even with a Bounded Delay Model derived from a real industrial library.