Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Precise identification of the worst-case voltage drop conditions in power grid verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Maximum circuit activity estimation using pseudo-boolean satisfiability
Proceedings of the conference on Design, automation and test in Europe
Using SAT-based techniques in power estimation
Microelectronics Journal
Satisfiability models for maximum transition power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bounded delay timing analysis and power estimation using SAT
Microelectronics Journal
ILP based approach for input vector controlled (IVC) toggle maximization in combinational circuits
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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In this paper, we present a statistical method for estimating the peak power dissipation in very large scale integrated (VLSI) circuits. The method is based on the theory of extreme order statistics and its application to the probabilistic distributions of the cycle-by-cycle power consumption, the maximum-likelihood estimation, and the Monte-Carlo simulation. It enables us to predict the maximum power of a VLSI circuit in the set of constrained input vector pairs as well as the complete set of all possible input vector pairs. The simulation-based nature of the proposed method allows us to avoid the limitations of a gate-level delay model and a gate-level circuit structure. Most significantly, the proposed method produces maximum power estimates to satisfy user-specified error and confidence levels. Experimental results show that this method typically produces maximum power estimates within 5% of the actual value and with a 90% confidence level by only simulating less than 2500 input vectors