A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Maximum power estimation for CMOS circuits using deterministic and statistic approaches
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Estimation of Maximum Power-up Current
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Maximum circuit activity estimation using pseudo-boolean satisfiability
Proceedings of the conference on Design, automation and test in Europe
Using SAT-based techniques in power estimation
Microelectronics Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Dynamic power estimation is a critical requirement in the design of digital logic for effective design decision. The brute-force way of estimating the power is to apply all the possible input vectors. Since the complexity of modern integrated circuits follow Moore's trend this technique can no longer be applied for computationally efficient and accurate power estimation. In the literature different techniques are reported for estimating the power either by generating the worst power consuming input vector or by applying some probability based technique. We have attempted to generate input vectors that result in maximum possible toggling for combinational circuits. In this work, we have modeled combinational circuits using binary integer linear program(BILP) and solved it using the mixed integer linear programming solver CPLEX. Experimental results on ISCAS-85 benchmarks show that the input vectors generated by our methodology result into maximally possible toggling in the circuit for most of the benchmark circuits.