Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Resolving signal correlations for estimating maximum currents in CMOS combinational circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Worst case voltage drops in power and ground buses of CMOS VLSI circuits
Worst case voltage drops in power and ground buses of CMOS VLSI circuits
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Computing the maximum power cycles of a sequential circuit
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Extreme delay sensitivity and the worst-case switching activity in VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Accurate power estimation of CMOS sequential circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 1995 IEEE ASIC conference
K2: an estimator for peak sustainable power of VLSI circuits
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Effects of delay models on peak power estimation of VLSI sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Automatic test generation using genetically-engineered distinguishing sequences
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Pareto-optimal hardware for digital circuits using SPEA
IEA/AIE'2005 Proceedings of the 18th international conference on Innovations in Applied Artificial Intelligence
Power estimation starategies for a low-power security processor
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
RT-level vector selection for realistic peak power simulation
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Maximum circuit activity estimation using pseudo-boolean satisfiability
Proceedings of the conference on Design, automation and test in Europe
Using SAT-based techniques in power estimation
Microelectronics Journal
Satisfiability models for maximum transition power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
LFSR based stream ciphers are vulnerable to power attacks
INDOCRYPT'07 Proceedings of the cryptology 8th international conference on Progress in cryptology
Bounded delay timing analysis and power estimation using SAT
Microelectronics Journal
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