K2: an estimator for peak sustainable power of VLSI circuits
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Effects of delay models on peak power estimation of VLSI sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Estimation of power sensitivity in sequential circuits with power macromodeling application
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Peak power estimation using genetic spot optimization for large VLSI circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
On mixture density and maximum likelihood power estimation via expectation-maximization
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Least-square estimation of average power in digital CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Tool for Activity Estimation in FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Monte-Carlo Approach for Power Estimation in Sequential Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Finding Stress Patterns in Microprocessor Workloads
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Generating power-hungry test programs for power-aware validation of pipelined processors
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Decomposition-based vectorless toggle rate computation for FPGA circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A precise high-level power consumption model for embedded systems software
EURASIP Journal on Embedded Systems
Finding extreme behaviors in microprocessor workloads
Transactions on High-Performance Embedded Architectures and Compilers IV
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The existence of near-closed sets makes the power estimation of sequential circuits more complicated and time consuming. If caution is not taken, the Monte Carlo-based power estimation techniques for sequential circuits can wrongly terminate the simulation with undesired results. In this paper, we have developed a strategy for a statistical power estimation technique to take into account the possible existence of near-closed sets. We propose an algorithm that partitions states into near-closed sets, if they do exist, and a technique that reduces the computation time of the probabilities of states if state transition graph (STG) is available. If STG is not available, we propose a Monte Carlo-based technique with a warm-up period. The results show that the partitioning algorithm also serves as a detector that signifies whether there may exist near-closed sets. The computation time of state probability can be reduced up to 50% in cases when near-closed sets are present. The relative error of the estimated individual node activity by the Monte Carlo-based technique with a warm-up period is within 3% of the result of long run simulation.