Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Estimation of circuit activity considering signal correlations and simultaneous switching
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Accurate power estimation of CMOS sequential circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 1995 IEEE ASIC conference
Effects of correlations on accuracy of power analysis—an experimental study
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Efficient estimation of dynamic power consumption under a real delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Switching activity estimation using limited depth reconvergent path analysis
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Fast Power Estimation of Large Circuits
IEEE Design & Test
Switching activity analysis and pre-layout activity prediction for FPGAs
Proceedings of the 2003 international workshop on System-level interconnect prediction
Dual-transition glitch filtering in probabilistic waveform power estimation
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Using negative edge triggered ffs to reduce glitching power in FPGA circuits
Proceedings of the 44th annual Design Automation Conference
Physical synthesis toolkit for area and power optimization on fpgas
Physical synthesis toolkit for area and power optimization on fpgas
Estimation of average switching activity in combinational logic circuits using symbolic simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Probabilistic modeling of dependencies during switching activity analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate-level power estimation using tagged probabilistic simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Markov chain sequence generator for power macromodeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a novel and accurate method of estimating the toggle rates of signals in field-programmable gate array (FPGA)-based logic circuits without the use of simulation vectors. Compared to previous vectorless techniques, our approach provides improved accuracy-of-results, especially for individual signals, which could be leveraged by computer-aided design (CAD) tools for performing power optimization of logic circuits. Increased accuracy is achieved by using stochastic methods that estimate the transition densities at FPGA logic elements while accounting for both spatial and temporal correlation of logic signals. Spatial correlation is calculated by leveraging a unique XOR-based decomposition technique that provides both accurate results and fast computation times. We also consider the delay information of implemented circuits, providing for a comprehensive treatment of glitches, including the effects of inertial limits on power dissipation. Our toggle-rate estimation approach has been tested on a commonly used set of Microelectronic Center of North Carolina circuits, as well as a set of industrial circuits targeted to Altera Stratix II FPGAs. Results show that our techniques provide a three times lower percent error, while maintaining a low processing time, when compared to two existing techniques: the vectorless estimation tool shipped with the commercial Quartus II 8.0 CAD tool, and the ACE v2.0 academic tool produced from the University of British Columbia, Vancouver, BC, Canada.