Switching activity analysis considering spatiotemporal correlations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
EURO-DAC '94 Proceedings of the conference on European design automation
Efficient power estimation for highly correlated input streams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient estimation of dynamic power consumption under a real delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Low Power Digital CMOS Design
Gate-level power estimation using tagged probabilistic simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Probabilistic gate-level power estimation using a novel waveform set method
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Decomposition-based vectorless toggle rate computation for FPGA circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Existing gate-level probabilistic approaches to power estimation fail to accurately model the glitch filtering by inertial delays. This effect has an impact on the power dissipation of a circuit and should not be neglected, especially for dynamic power estimation of circuits with dynamic power optimization. We propose a new glitch filtering analysis using the dual-transition probability that captures the states of a node at two different time instances. Experiments show that probabilistic simulation and the tagged probability simulation (TPS) techniques, when enhanced by the dual-transition analysis, provide more consistent power estimation. For circuits with a large component of glitch power, up to 29% improvement in the estimation accuracy is obtained.