G-vector: A New Model for Glitch Analysis in Logic Circuits
Journal of VLSI Signal Processing Systems
Dependency preserving probabilistic modeling of switching activity using bayesian networks
Proceedings of the 38th annual Design Automation Conference
Power analysis techniques for SoC with improved wiring models
Proceedings of the 2002 international symposium on Low power electronics and design
Power estimation of sequential circuits using hierarchical colored hardware petri net modeling
Proceedings of the 2002 international symposium on Low power electronics and design
A fast and accurate delay dependent method for switching estimation of large combinational circuits
Journal of Systems Architecture: the EUROMICRO Journal
Approximation Algorithms for the Maximum Power Consumption Problem on Combinatorial Circuits
ISAAC '00 Proceedings of the 11th International Conference on Algorithms and Computation
Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Switching activity estimation of VLSI circuits using Bayesian networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Petri net modeling of gate and interconnect delays for power estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Dual-transition glitch filtering in probabilistic waveform power estimation
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Proceedings of the 41st annual Design Automation Conference
Probabilistic gate-level power estimation using a novel waveform set method
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Satisfiability models for maximum transition power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic power estimation for deep submicron circuits with process variation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Decomposition-based vectorless toggle rate computation for FPGA circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A timing-dependent power estimation framework considering coupling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cascaded Bayesian inferencing for switching activity estimation with correlated inputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A theoretical probabilistic simulation framework for dynamic power estimation
Proceedings of the International Conference on Computer-Aided Design
Statistical full-chip total power estimation considering spatially correlated process variations
Integration, the VLSI Journal
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In this paper, we present a probabilistic simulation technique to estimate the power consumption of a CMOS circuit under a general delay model. This technique is based on the notion of a tagged (probability) waveform, which models the set of all possible events at the output of each circuit node. Tagged waveforms are obtained by partitioning the logic waveform space of a circuit node according to the initial and final values of each logic waveform and compacting all logic waveforms in each partition by a single tagged waveform. To improve the efficiency of tagged probabilistic simulation, only tagged waveforms at the circuit inputs are exactly computed. The tagged waveforms of the remaining nodes are computed using a compositional scheme that propagates the tagged waveforms from circuit inputs to circuit outputs. We obtain significant speed up over explicit simulation methods with an average error of only 6%. This also represents a factor of 2-3× improvement in accuracy of power estimates over previous probabilistic simulation approaches