Probabilistic reasoning in intelligent systems: networks of plausible inference
Probabilistic reasoning in intelligent systems: networks of plausible inference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Probabilistic analysis of large finite state machines
DAC '94 Proceedings of the 31st annual Design Automation Conference
Power estimation methods for sequential logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power estimation in sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Statistical estimation of average power dissipation in sequential circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Theoretical bounds for switching activity analysis in finite-state machines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Dependency preserving probabilistic modeling of switching activity using bayesian networks
Proceedings of the 38th annual Design Automation Conference
Power estimation for large sequential circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Probabilistic Networks and Expert Systems
Probabilistic Networks and Expert Systems
Estimation of state line statistics in sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Proceedings of the 2003 international symposium on Low power electronics and design
Switching activity estimation of VLSI circuits using Bayesian networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment
Proceedings of the 41st annual Design Automation Conference
Any-time probabilistic switching model using bayesian networks
Proceedings of the 2004 international symposium on Low power electronics and design
A timing-aware probabilistic model for single-event-upset analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cascaded Bayesian inferencing for switching activity estimation with correlated inputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Loopy belief propagation for approximate inference: an empirical study
UAI'99 Proceedings of the Fifteenth conference on Uncertainty in artificial intelligence
An importance sampling algorithm based on evidence pre-propagation
UAI'03 Proceedings of the Nineteenth conference on Uncertainty in Artificial Intelligence
Probabilistic modeling of dependencies during switching activity analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate-level power estimation using tagged probabilistic simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sequence compaction for power estimation: theory and practice
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A timing-aware probabilistic model for single-event-upset analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Probabilistic error modeling for nano-domain logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose a novel, nonsimulative probabilistic model for switching activity in sequential circuits, capturing both spatio-temporal correlations at internal nodes and higher order temporal correlations due to feedback. This model, which we refer to as the temporal dependency model (TDM), can be constructed from the logic structure and is shown to be a dynamic Bayesian network. Dynamic Bayesian networks are extremely powerful in modeling high order temporal, as well as spatial, correlations; TDM is an exact model for the underlying conditional independencies. The attractive feature of this graphical representation of the joint probability function is not only that it makes the dependency relationships amongst nodes explicit, but it also serves as a computational mechanism for probabilistic inference. We report average errors in switching probability of 0.006, with errors tightly distributed around mean error values, on ISCAS'89 benchmark circuits involving up to 10000 signals.