Power estimation for large sequential circuits

Authors:
Joseph N. Kozhaya;Farid N. Najm
Affiliations:
Univ. of Illnois, Urban-Champaign;Univ. of Illnois, Urban-Champaign
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2001

Citing 0
Cited 4

Power estimation of sequential circuits using hierarchical colored hardware petri net modeling

Proceedings of the 2002 international symposium on Low power electronics and design
Petri net modeling of gate and interconnect delays for power estimation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks

Proceedings of the 41st annual Design Automation Conference
Efficient algorithms for multilevel power estimation of VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

A power estimation approach is presented in which blocks of consecutive vectors are selected at random from a user-supplied realistic input vector set and the circuit is simulated for each block starting from an unknown state. This leads to two (upper and lower) bounds on the desired power value which can be quite tight (under 10% difference between the two in many cases). As a result, the power dissipation is obtained by simulating only a fraction of the potentially very large vector set.