Hierarchies in Coloured Petri Nets
APN 90 Proceedings on Advances in Petri nets 1990
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Switching activity analysis considering spatiotemporal correlations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Coloured Petri nets: basic concepts, analysis methods and practical use, vol. 2
Coloured Petri nets: basic concepts, analysis methods and practical use, vol. 2
New approach in gate-level glitch modelling
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Efficient estimation of dynamic power consumption under a real delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Efficient switching activity simulation under a real delay model using a bitparallel approach
DATE '99 Proceedings of the conference on Design, automation and test in Europe
High-level power estimation with interconnect effects
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Power-simulation of cell based ASICs: accuracy-and performance trade-offs
Proceedings of the conference on Design, automation and test in Europe
Dependency preserving probabilistic modeling of switching activity using bayesian networks
Proceedings of the 38th annual Design Automation Conference
Power estimation for large sequential circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Petri net modeling of gate and interconnect delays for power estimation
Proceedings of the 39th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate-level power estimation using tagged probabilistic simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using colored petri nets to predict future states in agent-based scheduling and planning systems
Multiagent and Grid Systems - Advances in Agent-mediated Automated Negotiations
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Switching activity estimation is an important step in average power estimation of VLSI circuits at the gate level. In this paper, we present a novel approach based on Petri net modeling for real delay switching activity and power estimation of CMOS circuits, considering both gate and interconnect delays. We propose a new type of Petri net called hierarchical colored hardware Petri net (HCHPN), which accurately captures the spatial and temporal correlations in modeling switching activity. The logic circuit is first modeled as a gate signal graph (GSG) which is then converted into the corresponding HCHPN and simulated as a Petri net to obtain the switching activity estimates and the power values. The proposed method is accurate and fast compared to other simulative methods. Experimental results are provided for ISCAS '85 and ISCAS'89 benchmark circuits and compared with the commercial tools, PowerMill, and Prime Power.