A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Efficient estimation of dynamic power consumption under a real delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Efficient switching activity simulation under a real delay model using a bitparallel approach
DATE '99 Proceedings of the conference on Design, automation and test in Europe
High-level power estimation with interconnect effects
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Dependency preserving probabilistic modeling of switching activity using bayesian networks
Proceedings of the 38th annual Design Automation Conference
PowerPlay-Fast Dynamic Power Estimation Based on Logic Simulation
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Petri net modeling of gate and interconnect delays for power estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Cascaded Bayesian inferencing for switching activity estimation with correlated inputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ICATPN'06 Proceedings of the 27th international conference on Applications and Theory of Petri Nets and Other Models of Concurrency
Petri-Net-Based coordination algorithms for grid transactions
ISPA'04 Proceedings of the Second international conference on Parallel and Distributed Processing and Applications
A retargetable environment for power-aware code evaluation: an approach based on coloured petri net
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit is converted into a HCHPN and simulated as a Petri net to get the switching activity estimate and thus the power values. The method is accurate and is significantly faster than other simulative methods. The HCHPN yields an average error of 4.9% with respect to Hspice for the ISCAS '85 benchmark circuits. The per-pattern simulation time is about 46 times lesser than PowerMill.