A retargetable environment for power-aware code evaluation: an approach based on coloured petri net

Authors:
Meuse N. O. Junior;Paulo Maciel;Ricardo Lima;Angelo Ribeiro;Cesar Oliveira;Adilson Arcoverde;Raimundo Barreto;Eduardo Tavares;Leornado Amorin
Affiliations:
Centro de Informática (CIn), Universidade Federal de Pernambuco (UFPE), Brazil;Centro de Informática (CIn), Universidade Federal de Pernambuco (UFPE), Brazil;Departamento de Sistemas Computacionais, Universidade de Pernambuco (UPE), Brazil;Centro de Informática (CIn), Universidade Federal de Pernambuco (UFPE), Brazil;Departamento de Sistemas Computacionais, Universidade de Pernambuco (UPE), Brazil;Centro de Informática (CIn), Universidade Federal de Pernambuco (UFPE), Brazil;Centro de Informática (CIn), Universidade Federal de Pernambuco (UFPE), Brazil;Centro de Informática (CIn), Universidade Federal de Pernambuco (UFPE), Brazil;Centro de Informática (CIn), Universidade Federal de Pernambuco (UFPE), Brazil
Venue:
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2005

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Abstract

This paper presents an approach for power-aware code exploration, through an analysis mechanism based on Coloured Petri Net (CPN). Given a code under interest and a CPN description of architecture, a CPN model of application (processor + code) is generated. Coloured Petri Net models allow the application of widespread analysis approaches, for instance simulation and/or state-space exploration. Additionally, this work presents a framework where a widespread CPN tool is applied to processor architecture description, model validation and analysis by simulation. A Petri net integration environment was extended in order to support specific power-aware analysis. In the present approach, such framework is focused on the Embedded Systems context, covering pipeline-less and simplescalar architectures.