Generation of software tools from processor descriptions for hardware/software codesign
DAC '97 Proceedings of the 34th annual Design Automation Conference
Fast out-of-order processor simulation using memoization
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Insulin: An Instruction Set Simulation Environment
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
An efficient retargetable framework for instruction-set simulation
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
DynamoSim: a trace-based dynamically compiled instruction set simulator
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A retargetable framework for instruction-set architecture simulation
ACM Transactions on Embedded Computing Systems (TECS)
The SimCore/Alpha Functional Simulator
WCAE '04 Proceedings of the 2004 workshop on Computer architecture education: held in conjunction with the 31st International Symposium on Computer Architecture
A retargetable environment for power-aware code evaluation: an approach based on coloured petri net
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) simulators have been reported, the more relevant micro-architecture simulators, which are capable of modeling the detailed machine features such as cache organization, branch prediction and out-of-order scheduler, have not be equipped with retargetability. In this paper, we propose a new methodology that can generate completed micro-architecture simulators from the abstract ISA and the application binary interface (ABI) specification. We demonstrate our methodology by the development of a tool that can automatically port the SimpleScalar toolset, the de facto standard for micro-architecture simulation, to any processor.