The SimCore/Alpha Functional Simulator

Authors:
Kenji Kise;Takahiro Katagiri;Hiroki Honda;Toshitsugu Yuba
Affiliations:
The University of Electro-Communications and Japan Science and Technology Agency (JST);The University of Electro-Communications and Japan Science and Technology Agency (JST);The University of Electro-Communications;The University of Electro-Communications
Venue:
WCAE '04 Proceedings of the 2004 workshop on Computer architecture education: held in conjunction with the 31st International Symposium on Computer Architecture
Year:
2004

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Abstract

We have developed a function-level processor simulator, SimCore/Alpha Functional Simulator Version 2.0 (SimCore Version 2.0), for processor architecture research and processor education. This paper describes the design and implementation of SimCore Version 2.0. The main features of SimCore Version 2.0 are as follows: (1) It offers many functions as a function-level simulator. (2) It is implemented compactly with 2,800 lines in C++. (3) It separates the function of the program loader. (4) No global variable is used, and so it improves the readability and function. (5) It offers a powerful verification mechanism. (6) It operates on many platforms. (7) Compared with sim-fast in the SimpleScalar Tool Set, SimCore Version 2.0 attains a 19% improvement in simulation speed.