Petri net modeling of gate and interconnect delays for power estimation
Proceedings of the 39th annual Design Automation Conference
Power estimation of sequential circuits using hierarchical colored hardware petri net modeling
Proceedings of the 2002 international symposium on Low power electronics and design
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Petri net modeling of gate and interconnect delays for power estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
GlitchMap: an FPGA technology mapper for low power considering glitches
Proceedings of the 44th annual Design Automation Conference
FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation
Proceedings of the 46th Annual Design Automation Conference
Efficient algorithms for multilevel power estimation of VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents an accurate estimation of signal activity at the internal and output nodes of static and domino CMOS combinational logic circuits. The methodology is based on a stochastic model of logic signals and takes correlations and simultaneous switching of signals at logic gate inputs into consideration. In static combinational logic synthesis, in order to minimize spurious transitions due to finite propagation delays, it is crucial to balance all signal paths and to reduce the logic depth. As a result of balancing delays through different paths, the inputs to logic gates may switch at approximately the same time. We have developed and implemented a technique to calculate signal probability and switching activity of static CMOS combinational logic circuits. Experimental results show that if simultaneous switching is not considered, the switching activities at the internal nodes can be off by more than 100% compared to simulation based techniques. In contrast, our technique is on the average within 2% of logic simulation results. On the other hand, domino circuits are free of spurious transitions. Based on the precharge scheme of domino circuits, a technique for estimation of signal activity is presented. The results are within 1% of logic simulation results