New approach in gate-level glitch modelling

  • Authors:
  • D. Rabe;W. Nebel

  • Affiliations:
  • Carl von Ossietzky University Oldenburg, FB 10-Department of Computer Science, D-26111 Oldenburg, Germany;OFFIS, Escherweg 2, D-26121 Oldenburg, Germany

  • Venue:
  • EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
  • Year:
  • 1996

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Abstract