Hierarchies in Coloured Petri Nets
APN 90 Proceedings on Advances in Petri nets 1990
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
Coloured Petri nets: basic concepts, analysis methods and practical use, vol. 2
Coloured Petri nets: basic concepts, analysis methods and practical use, vol. 2
New approach in gate-level glitch modelling
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Efficient estimation of dynamic power consumption under a real delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Computation of lower bounds for switching activity using decision theory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On average power dissipation and random pattern testability of CMOS combinational logic networks
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Efficient switching activity simulation under a real delay model using a bitparallel approach
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Power-simulation of cell based ASICs: accuracy-and performance trade-offs
Proceedings of the conference on Design, automation and test in Europe
Dependency preserving probabilistic modeling of switching activity using bayesian networks
Proceedings of the 38th annual Design Automation Conference
SYCLOP: Synthesis of CMOS Logic for Low Power Applications
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Design/CPN - A Computer Tool for Coloured Petri Nets
TACAS '97 Proceedings of the Third International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Power estimation of sequential circuits using hierarchical colored hardware petri net modeling
Proceedings of the 2002 international symposium on Low power electronics and design
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Switching activity estimation is an important step in power estimation of digital VLSI circuits. While simulation yields accurate results, it is time consuming. In this paper, we propose a new technique based on Petri nets for real-delay switching activity estimation that yields the same accuracy as simulation, but is significantly faster in computation. We introduce a new type of Petri net called Hierarchical Colored Hardware Petri Net (HCHP-Net). The gate-level circuit is first transformed into a directed acyclic graph called, GSDAG, in which both the gates as well as the signals correspond to the nodes in the graph. The GSDAG is then mapped onto a corresponding HCHP-Net which is then simulated using a Petri net simulator. Experimental results for ISCAS '85 circuits are presented. The method replicates exactly the switching activity results for real-delay models produced by HSPICE and PowerMill. However, the per-pattern simulation time is about 51 times faster than the Synopsys PowerMill and 8900 times faster than the Avanti HSPICE.