Least-square estimation of average power in digital CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Real Delay Switching Activity Simulator based on Petri net Modeling
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A path based modeling approach for dynamic power estimation
Proceedings of the 17th ACM Great Lakes symposium on VLSI
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Accurate switching-activity estimation is crucial for power budgeting. It is impractical to obtain an accurate estimate by simulating the circuit for all possible inputs. An alternate approach would be to compute tight bounds for the switching activity. In this paper, we propose a nonsimulative decision theoretic method to compute the lower bound for switching activity. First, we show that the switching activity can be modeled as the decision error of an abstract two-class problem. It is shown that the Bayes error L* is a lower bound for the switching activity. Further, we improve L* to obtain a tighter bound L/sub 1/, which is based on the one-nearest neighbor classification error. The proposed lower bounds are used for switching-activity characterization at the register transfer (RT) level. Experimental results for the RT-level switching-activity estimates for ISCAS'85 circuits are presented. This technique is simple and fast and produces accurate estimates.