Discrete-time signal processing
Discrete-time signal processing
The probability of error detection in sequential circuits using random test vectors
Journal of Electronic Testing: Theory and Applications
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
A methodology for efficient estimation of switching activity in sequential logic circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Exact and approximate methods for calculating signal and transition probabilities in FSMs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Probabilistic analysis of large finite state machines
DAC '94 Proceedings of the 31st annual Design Automation Conference
Statistical estimation of the switching activity in digital circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Power estimation in sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
One-Dimensional Digital Signal Processing
One-Dimensional Digital Signal Processing
Proceedings of the 41st annual Design Automation Conference
Power minimization for dynamically reconfigurable FPGA partitioning
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
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In this article, we present a simulation-based technique for estimation of signal statistics (switching activity and signal probability) at the flip-flop output nodes (state signals) of a general sequential circuit. Apart from providing an estimate of the power consumed by the flip-flops, this information is needed for calculating power in the combinational portion of the circuit. The statistics are computed by collecting samples obtained from fast RTL simulation of the circuit under input sequences that are either randomly generated or independently selected from user-specified pattern sets. An important advantage of this approach is that the desired accuracy can be specified up front by the user; with some approximation, the algorithm iterates until the specified accuracy is achieved. This approach has been implemented and tested on a number of sequential circuits and has been shown to handle very large sequential circuits that can not be handled by other existing methods, while using a reasonable amount of CPU time and memory (the circuit s38584.1, with 1426 flip-flops, can be analyzed in about 10 minutes).