Probabilistic reasoning in intelligent systems: networks of plausible inference
Probabilistic reasoning in intelligent systems: networks of plausible inference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Switching activity analysis considering spatiotemporal correlations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Improving the accuracy of circuit activity measurement
DAC '94 Proceedings of the 31st annual Design Automation Conference
Efficient estimation of dynamic power consumption under a real delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Dependency preserving probabilistic modeling of switching activity using bayesian networks
Proceedings of the 38th annual Design Automation Conference
Least-square estimation of average power in digital CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Probabilistic Networks and Expert Systems
Probabilistic Networks and Expert Systems
Fast Power Estimation of Large Circuits
IEEE Design & Test
Probabilistic modeling of dependencies during switching activity analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate-level power estimation using tagged probabilistic simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Any-time probabilistic switching model using bayesian networks
Proceedings of the 2004 international symposium on Low power electronics and design
Causal probabilistic input dependency learning for switching model in VLSI circuits
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Proceedings of the 41st annual Design Automation Conference
Probabilistic gate-level power estimation using a novel waveform set method
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Mapping for better than worst-case delays in LUT-based FPGA designs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Thermal switching error versus delay tradeoffs in clocked QCA circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stochastic power/ground supply voltage prediction and optimization via analytical placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A timing-aware probabilistic model for single-event-upset analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cascaded Bayesian inferencing for switching activity estimation with correlated inputs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sequential algorithm for low-power encoding internal states of finite state machines
Journal of Computer and Systems Sciences International
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Switching activity estimation is an important aspect of power estimation at circuit level. Switching activity in a node is temporally correlated with its previous value and is spatially correlated with other nodes in the circuit. It is important to capture the effects of such correlations while estimating the switching activity of a circuit. In this paper, we propose a new switching probability model for combinational circuits that uses a logic-induced directed-acyclic graph (LIDAG) and prove that such a graph corresponds to a Bayesian network (BN), which is guaranteed to map all the dependencies inherent in the circuit. BNs can be used to effectively model complex conditional dependencies over a set of random variables. The BN inference schemes serve as a computational mechanism that transforms the LIDAG into a junction tree of cliques to allow for probability propagation by local message passing. The proposed approach is accurate and fast. Switching activity estimation of ISCAS and MCNC circuits with random and biased input streams yield high accuracy (average mean error = 0.002) and low computational time (average elapsed time including CPU, memory access and I/O time for the benchmark circuits = 3.93s).