Power estimation methods for sequential logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Switching activity estimation of VLSI circuits using Bayesian networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Any-time probabilistic switching model using bayesian networks
Proceedings of the 2004 international symposium on Low power electronics and design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Multimode power modeling and maximum-likelihood estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
FSM State Assignment Methods for Low-Power Design
CISIM '07 Proceedings of the 6th International Conference on Computer Information Systems and Industrial Management Applications
Integration, the VLSI Journal
A method for minimizing Moore finite-state machines by merging two states
Journal of Computer and Systems Sciences International
Faster power estimation of CMOS designs using vector compaction - a fractal approach
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
NOVA: state assignment of finite state machines for optimal two-level logic implementation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Markov chain sequence generator for power macromodeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimization of mealy finite-state machines by internal states gluing
Journal of Computer and Systems Sciences International
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A heuristic method for encoding internal states (state assignment) of finite state machines (FSMs) so as to reduce their power consumption is proposed. A feature of the proposed approach is that the state assignment procedure takes into account the activity function of the memory elements when the FSM transits from a current state to other states that have already been encoded. A procedure for determining the power consumption of the FSM based on the codes of its internal states and probabilities of appearance of units at each input of the FSM is described. Experiments showed that the proposed approach makes it possible to reduce the power consumption of the FSM by 39% on the average compared with the NOVA algorithm and sometimes by 68%. In conclusion, the possibilities of improving the performance of the proposed algorithm in the synthesis of a specific FSM are discussed and promising directions of further research are indicated.