On the Reduction of Superfluous States in a Sequential Machine
Journal of the ACM (JACM)
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Minimization of incompletely specified mealy finite-state machines by merging two internal states
Journal of Computer and Systems Sciences International
Sequential algorithm for low-power encoding internal states of finite state machines
Journal of Computer and Systems Sciences International
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A problem of minimization of Mealy finite-state machines that is common in synthesizing digital devices on programmable logic devices is considered. The proposed approach uses an operation of gluing two states and represents the finite-state machine as a list of transitions. Cases when gluing two states generates wait states are described. Algorithms that minimize the number of internal states, the number of transitions and input variables of Mealy finite-state machines are given. The experimental results showed that when used to implement finite-state machines on programmable logic devices, the proposed method helps decrease the implementation cost 1.31 times on average and 3 times at best. Topical directions for further study of finite-state machines minimization methods are given.