A new model for computation of probabilistic testability in combinational circuits
Integration, the VLSI Journal
Switching activity analysis considering spatiotemporal correlations
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Efficient power estimation for highly correlated input streams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Switching activity estimation of VLSI circuits using Bayesian networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-transition glitch filtering in probabilistic waveform power estimation
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Gate-level power estimation using tagged probabilistic simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Probabilistic gate-level power estimation using a novel waveform set method
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Statistical full-chip total power estimation considering spatially correlated process variations
Integration, the VLSI Journal
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Consideration of pairs of transition in probabilistic simulation allows power estimation for digital circuits in which inertial delays can filter glitches [5]. However, the merit of the method is not fully realized because of the way probabilistic simulation approximates spatial correlations of signals in the presence of delays. In this paper, we use supergate partitions (enclosing reconvergent fanouts) and timed Boolean functions (TBF) to obtain the dual-transition probabilities that correctly deal with glitches and filtering as they affect power estimation. Experimental results on ISCAS驴85 benchmarks show significant improvements in estimation accuracy as the average estimation error on total power consumption remains under 5%.