A new model for computation of probabilistic testability in combinational circuits

Corolla based circuit partitioning and resynthesis

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference

Search space reduction through clustering in test generation

EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation

Power minimization in IC design: principles and applications

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation

Journal of Electronic Testing: Theory and Applications

Fast statistical timing analysis by probabilistic event propagation

Proceedings of the 38th annual Design Automation Conference

A New Framework for Designing: Built-in Test Multichip Modules with Pipelined Test Strategy

IEEE Design & Test

Characteristic polynomial method for verification and test of combinational circuits

VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication

A Fault-Independent Transitive Closure Algorithm for Redundancy Identification

VLSID '03 Proceedings of the 16th International Conference on VLSI Design

Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis

ICCD '05 Proceedings of the 2005 International Conference on Computer Design

Novel probabilistic combinational equivalence checking

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Scalable sampling methodology for logic simulation: reduced-ordered Monte Carlo

Proceedings of the International Conference on Computer-Aided Design