Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A new model for computation of probabilistic testability in combinational circuits
Integration, the VLSI Journal
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
A Small Test Generator for Large Designs
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Method for Reducing the Search Space in Test Pattern Generation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
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Combinational test pattern generation (TPG) is basically a search ina finite state space. In general, the search is performed in abranch-and-bound fashion. The branch-and-bound search builds a decision treeusing two basic operations: decision making andbacktracking. The size of the decision tree, and hencethe efficiency of the branch-and-bound search, is directly dependent on thenumber of decisions made. This paper proposes a set of novel techniques forreducing the number of decisions and the size of the decision space. Thesetechniques work directly on the maximum number of potential ways ofjustifying a given logical assignment. This maximum number is reduced byexploiting the properties of prime-and-irredundantcovers. These same properties are also used to reduce the number ofbacktracks by implying a maximum number of necessaryassignments. The reduction of the number of decisions and theidentification of a maximum of necessary assignments make the proposed TPGmethod highly efficient as demonstrated by experimental results. This paperalso proposes a novel combination of prime-and-irredundant cover extractionand transitive closure computation for a more efficient TPG process.