A new model for computation of probabilistic testability in combinational circuits
Integration, the VLSI Journal
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
A Course in Simulation
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
SS '01 Proceedings of the 34th Annual Simulation Symposium (SS01)
Accurate and scalable reliability analysis of logic circuits
Proceedings of the conference on Design, automation and test in Europe
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
The influence of variables on Boolean functions
SFCS '88 Proceedings of the 29th Annual Symposium on Foundations of Computer Science
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Tomographic Testing and Validation of Probabilistic Circuits
ETS '11 Proceedings of the 2011 Sixteenth IEEE European Test Symposium
Estimation of component criticality in early design steps
IOLTS '11 Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium
Generalized Boolean symmetries through nested partition refinement
Proceedings of the International Conference on Computer-Aided Design
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Monte Carlo (MC) simulation plays a key role in EDA as the gold standard against which heuristics are measured. It is also an important stand-alone technique for statistics-based tasks like power estimation and reliability analysis. Accurate simulation requires large sample sets and long runtimes, which can be hard to achieve with conventional MC. We propose an approach called Reduced-Ordered Monte Carlo (ROMC), which improves simulation efficiency, while still producing accurate results. ROMC takes advantage of the (partial) redundancy inherent in digital signals. It prioritizes input signals based on their observability at the outputs, and combines inputs based on a compatibility property that enables them to share samples. Experimental results are presented which demonstrate that the ROMC methodology can decrease simulation runtime by several orders of magnitude.