Scalable sampling methodology for logic simulation: reduced-ordered Monte Carlo
Proceedings of the International Conference on Computer-Aided Design
Survey of Stochastic Computing
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
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Some emerging technologies for building computers depend on components and signals whose behavior, under normal or fault conditions, is probabilistic. Examples include stochastic and quantum computing circuits, and conventional nano electronic circuits subject to design, manufacturing or environmental errors. Problems common to these technologies are testing and validation, which require determining whether observed non-deterministic behavior is within acceptable limits. Traditional solution methods rely on the determinism of operations performed by the circuit under test, and are not applicable to probabilistic circuits, where signals are often described by probability distributions. We introduce a generic methodology for testing probabilistic circuits by approximating signal probability distributions using tomograms, which aggregate the outcomes of multiple, repeated test measurements. While the name comes from quantum computation, tomography is applicable to both quantum and non-quantum probabilistic circuits, as we demonstrate. Our methodology makes use of fault or error models that allow handling of large and complex circuits. We report the first experimental results on the tomographic testing of quantum and stochastic circuits.