Test generation for digital systems
Fault-tolerant computing: theory and techniques; vol. 1
A new model for computation of probabilistic testability in combinational circuits
Integration, the VLSI Journal
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
IEEE Transactions on Computers
IEEE Spectrum
An efficient partitioning strategy for pseudo-exhaustive testing
DAC '93 Proceedings of the 30th international Design Automation Conference
A probabilistic multicommodity-flow solution to circuit clustering problems
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Shift Register Sequences
Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Area efficient pipelined pseudo-exhaustive testing with retiming
DAC '96 Proceedings of the 33rd annual Design Automation Conference
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A novel test strategy, the Loop Testing Architecture (LTA), is introduced to reduce aliasing probability and testing time for multichip modules. This is accomplished by connecting cascadable built-in testers (CBITs) in neighboring pipelined stages to increase the length of the test suites. Fundamental properties of the LTA supporting randomness in the generated test patterns (state coverage) and the asymptotic aliasing probability are presented. Results on two small-scale multiprocessor configurations show that the aliasing probability in analyzing signatures is comparable to that of an MLFSR but with fairly low area overhead; compared with the circular self-test path technique, less testing time is required by LTA. Further evaluation of the potential capabilities provided by the LTA compared with boundary scan and other pipelined test scheduling approaches confirmed the usefulness of LTA as a framework for designing effective testable systems.