A new model for computation of probabilistic testability in combinational circuits
Integration, the VLSI Journal
A fast algorithm for finding dominators in a flowgraph
ACM Transactions on Programming Languages and Systems (TOPLAS)
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Dynamic load balancing of a multi-cluster simulator on a network of workstations
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
A partitioning-based logic optimization method for large scale circuits with Boolean matrix
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Speeding up technology-independent timing optimization by network partitioning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Congestion aware layout driven logic synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Synthesis of skewed logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integer linear programming-based synthesis of skewed logic circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
| Hi-index | 0.00 |
This paper introduces a circuit partitioning method based on analysis of reconvergent fanout. We consider a DAG model for a circuit. We define a corolla as a set of overlapping reconvergent fanout regions. We partition the DAG into a set of non-overlapping corollas and use the corollas to resynthesize the circuit. We show that resynthesis of large benchmark circuits consistently reduces transistor pairs and layout area while improving delay and testability.