A partitioning-based logic optimization method for large scale circuits with Boolean matrix

Authors:
Yuichi Nakamura;Takeshi Yoshimura
Affiliations:
C&C Research Laboratories, NEC Corporation, Miyazaki, Miyamae-ku, Kawasaki 216, Japan;C&C Research Laboratories, NEC Corporation, Miyazaki, Miyamae-ku, Kawasaki 216, Japan
Venue:
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Year:
1995

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Abstract