Power analysis techniques for SoC with improved wiring models

Authors:
Takeshi Sakamoto;Takashi Yamada;Mamoru Mukuno;Yoshifumi Matsushita;Yasoo Harada;Hiroto Yasuura
Affiliations:
SANYO Electric, Gifu, Japan;SANYO Electric, Gifu, Japan;SANYO Electric, Gifu, Japan;SANYO Electric, Gifu, Japan;SANYO Electric, Gifu, Japan;Kyushu University, Kasuga, Japan
Venue:
Proceedings of the 2002 international symposium on Low power electronics and design
Year:
2002

A survey of power estimation techniques in VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Gate-level timing verification using waveform narrowing

EURO-DAC '94 Proceedings of the conference on European design automation
Power minimization in IC design: principles and applications

ACM Transactions on Design Automation of Electronic Systems (TODAES)
An interconnect energy model considering coupling effects

Proceedings of the 38th annual Design Automation Conference
Power Aware Design Methodologies

Power Aware Design Methodologies
Gate-level power estimation using tagged probabilistic simulation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Hi-index	0.00

This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC).