Decomposition-based vectorless toggle rate computation for FPGA circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dimension-reducible Boolean functions based on affine spaces
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reducing the pressure on routing resources of FPGAs with generic logic chains
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
SOP restructuring by exploiting don't cares
Microprocessors & Microsystems
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This paper presents a novel XOR-based logic synthesis approach called functionally linear decomposition and synthesis (FLDS). This approach decomposes a logic function to expose an XOR relationship by using Gaussian elimination. It is fundamentally different from the traditional approaches to this problem, which are based on the work of Ashenhurst and Curtis. FLDS utilizes binary decision diagrams to efficiently represent logic functions, making it fast and scalable. This technique was tested on a set of 99 MCNC benchmarks, mapping each design into a network of four input lookup tables. On the 25 of the benchmarks, which have been classified by previous researchers as XOR-based logic circuits, our approach provides significant area savings. In comparison to the leading logic synthesis tools, ABC and BDS-PGA 2.0, FLDS produces XOR-based circuits with 25.3% and 18.8% smaller area, respectively. The logic circuit depth is also improved by 7.7% and 14.5%, respectively.