Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
On a New Boolean Function with Applications
IEEE Transactions on Computers
Switching Theory for Logic Synthesis
Switching Theory for Logic Synthesis
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Multi-level logic optimization
Logic Synthesis and Verification
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
A Polynomial Time Algorithm for Non-Disjoint Decomposition of Multiple-Valued Functions
ISMVL '04 Proceedings of the 34th International Symposium on Multiple-Valued Logic
The optimization of kEP-SOPs: Computational complexity, approximability and experiments
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Coping with Soft Errors in Asynchronous Burst-Mode Machines
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
On Projecting Sums of Products
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
Scalable don't-care-based logic optimization and resynthesis
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Cybernetics and Systems Analysis
Approximate logic synthesis for error tolerant applications
Proceedings of the Conference on Design, Automation and Test in Europe
On decomposing Boolean functions via extended cofactoring
Proceedings of the Conference on Design, Automation and Test in Europe
BDS: a BDD-based logic optimization system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing-driven logic bi-decomposition
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of SPP three-level logic networks using affine spaces
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Complexity of two-level logic minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logic Minimization and Testability of 2-SPP Networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DSD '12 Proceedings of the 2012 15th Euromicro Conference on Digital System Design
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In this paper we define and study the properties of a generalized Shannon expansion on non-disjoint subsets of the Boolean space. This expansion consists in projecting the original function onto several overlapping subsets. Since the logic can be distributed among the projection subsets, input combinations asserted by a subset may be exploited as don't cares for the other subsets. Our target is to exploit these don't cares to obtain more compact networks based on SOP expressions. In particular, we show how to take advantage of don't cares, derived from the projections, in two synthesis techniques, i.e., using a Boolean and an algebraic algorithm. Experimental results show that in the Boolean case 65% of the considered benchmarks achieve more compact area when implemented using projected don't cares. The benefit in the algebraic approach is reduced (35% of instances benefit from the proposed technique), even though there are examples with an interesting decrease of the area.